1. Field of the Invention
Embodiments of the present invention generally relate to a method of fabricating a flash memory cell having a split gate structure.
This application claims the benefit of Korean Patent Application No. 2003-65679, filed Sep. 22, 2003, the disclosure of which is hereby incorporated herein by reference in its entirety.
2. Description of the Related Art
A flash memory device is a nonvolatile memory device capable of retaining data after a power supply is cut off. A nonvolatile memory device can be highly-integrated by taking advantage of EPROM (erasable programmable read only memory) and/or EEPROM (electrically erasable programmable read only memory) technologies. A related art flash memory cell has a stack-gate structure including a tunnel oxide layer, a floating gate, an insulating layer, and a control gate, which are stacked on a semiconductor substrate between a source and a drain.
The stack-gate structure may be problematic, due to an over-erase phenomenon. In efforts to solve this over-erase problem, flash memory cells having a split gate structure have been suggested. Japanese Laid Open Disclosure No. 1999-284084 describes a method of fabricating a split gate structure using a LOCOS process. Japanese Laid Open Disclosure No. 1999-284084 by Otani Toshiharu has the title ‘NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND ITS MANUFACTURE’.
FIGS. 1A to 1E illustrate a method of fabricating a flash memory cell having a split gate structure. In FIG. 1A, a gate oxide layer 11, a first polysilicon layer 12, and a silicon nitride layer 13 are stacked on a semiconductor substrate 10. In FIG. 1B, by patterning the silicon nitride layer 13, a silicon nitride layer pattern 13A is formed having an opening 13B, exposing a portion of the first polysilicon layer 12. In FIG. 1C, a poly oxide layer 14 is formed by performing a LOCOS (local oxidation of silicon) process using the silicon nitride layer pattern 13A as an oxidation stop layer. A portion of the exposed first polysilicon layer 12 is consequently oxidized.
In FIG. 1D, a floating gate 12A is formed under the poly oxide layer 14 by removing the silicon nitride layer pattern 13A and etching the first polysilicon layer 12. The etching of the first polysilicon layer 12 uses the poly oxide layer 14 as an etch mask. In FIG. 1E, an oxide layer 15 is formed on the semiconductor substrate 10 and the poly oxide layer 14. A control gate 16, overlapping a portion of the floating gate 12A, is formed of a second polysilicon layer. Spacers 17 are formed on the sidewalls of the floating gate 12A and the control gate 16. Source/drain 18A, 18B are formed inside the semiconductor substrate 10. The oxide layer 15 functions as a tunnel oxide layer 15A in the region between the floating gate 12A and the control gate 16. The oxide layer 15 functions as a gate oxide layer 15B in the region between the semiconductor substrate 10 and the control gate 16.
There may be complications in the above described related art LOCOS process of fabricating a split gate structure. Specifically, there may be complications in forming the poly oxide layer 14 having a uniform thickness, as insulation between the floating gate 12A and the control gate 16. Further, there may be complications in the LOCOS process due to a heat budget. The thermal oxidation is performed at a temperature of about 800° C., which may cause a smiling effect to thicken the boundary of the gate oxide layer. This may result in degradation of cell characteristics, and consequential malfunctioning may occur during programming and erasing operations.
Many parasitic capacitors intrinsically exist in the flash memory cell having the split gate structure, fabricated in accordance with the related art. In FIG. 1E, a tunnel capacitor (Ct) is illustrated between the sidewalls of the control gate 16 and the floating gate 12A. A gate interlayer capacitor (Cip) is illustrated between the control gate 16 and the upper surface of the floating gate 12A. Further, a channel capacitor (Cc) is illustrated between the floating gate 12A and the semiconductor substrate 10. A source capacitor (Cs) is illustrated between the floating gate 12A and the source 18A.
The program operation of the flash memory cell having a split gate structure, as shown in FIG. 1E, is explained below. A high voltage is applied on the source 18A and a ground voltage is applied on the drain 18B. The electrons generated in the drain 18B, move to the source 18A through the channel region formed in the semiconductor substrate 10 when a program voltage is applied to the control gate 16. The program voltage is lower than the voltage applied on the source 18A and higher than the threshold voltage for the formation of the channel region. Some of the electrons moving to the source 18A are excited by the potential difference between the drain 18B and the floating gate 12A, coupled by the high voltage applied on the source 18A. These excited electrons are injected into the floating gate 12A. In other words, the program operation is performed by hot carrier injection into the floating gate 12A. Using FIG. 1E as an illustration a program coupling ratio (rp) can be represented by Equation 1.
                              r          p                =                              C1            +            C2                                C1            +            C2            +            C3            +            C4                                              [                  Equation          ⁢                                          ⁢          1                ]            
In Equation 1, ‘C1’, ‘C2’, ‘C3’, and ‘C4’ are the capacitance of the source capacitor (Cs), the capacitance of the channel capacitor (Cc), the capacitance of the tunnel capacitor (Ct), and the capacitance of the gate interlayer capacitor (Cip), respectively.
The erase operation of the flash memory cell, having a split gate structure, is explained below. If a high voltage is applied on the control gate 16, a ground voltage is applied on the source 18A, and a ground voltage is applied to the drain 18B. The electrons charged in the floating gate 12A are removed to the control gate 16 by the high voltage applied on the control gate 16. In other words, the electrons charged in the floating gate 12A are erased by a F-N (Fowler-Nordheim) tunneling effect. Using FIG. 1E as an illustration, an erase coupling ratio (rE) can be represented by Equation 2 with capacitances (C1, C2, C3, C4) of the parasitic capacitors (Cs, Cc, Ct, Cip).
                              r          E                =                              C3            +            C4                                C1            +            C2            +            C3            +            C4                                              [                  Equation          ⁢                                          ⁢          2                ]            
It is desirable to reduce the width ‘W’ of the poly oxide layer 14 with increased integration of a device. As shown in FIG. 1B, when the width of the exposed polysilicon layer 12 is reduced, the width of the opening 13B, provided for the formation of the poly oxide layer 14, is reduced. Accordingly, the thickness of the poly oxide layer 14, produced by the LOCOS process, is reduced. The reduction of the thickness of the poly oxide layer 14 increases the capacitance of the gate interlayer parasitic capacitor (Cip) between the control gate 16 and the floating gate 12A, thereby degrading device characteristics. In other words, if the capacitance of the gate interlayer capacitor (Cip), generated between the floating gate 12A and the control gate 16, is increased, the voltage applied on the floating gate 12A during programming is reduced, resulting in a decrease of program efficiency.